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| TNY375-380 TinySwitch-PK Family (R) Energy-Efficient, Off-Line Switcher With Enhanced Peak Power Performance Product Highlights Lowest System Cost with Enhanced Flexibility * Simple ON/OFF control, no loop compensation needed * Unique Peak Mode feature extends power range without increasing transformer size * Maximum frequency and current limit boosted at peak loads * Selectable current limit through BP/M capacitor value * Higher current limit extends maximum power in open frame * Lower current limit improves efficiency in enclosed adapters * Allows optimum TinySwitch-PK choice by swapping devices with no other circuit redesign * Tight I2f parameter tolerance reduces system cost * Maximizes MOSFET and magnetics power delivery * ON time extension - typically extends low line regulation range/ hold-up time to reduce input bulk capacitance * Self-biased: no bias winding required for TNY375-376; winding required for TNY377-380 * Frequency jittering reduces EMI filter costs * Optimized pin out eases pcb/external heatsinking * Quiet source-connected heatsink pins for low EMI Enhanced Safety and Reliability Features * Accurate hysteretic thermal shutdown with automatic recovery provides complete system level overload protection and eliminates need for manual reset * Auto-restart delivers <3% maximum power in short circuit and open loop fault conditions * Output overvoltage shutdown with optional Zener * Line undervoltage detect threshold set using a single resistor * Very low component count enhances reliability and enables single sided printed circuit board layout * High bandwidth provides fast turn on with no overshoot and excellent transient load response * Extended creepage between DRAIN and all other pins improves field reliability EcoSmart - Extremely Energy Efficient * Easily meets all global energy efficiency regulations * No-load <170 mW at 265 VAC without bias winding, <60 mW with bias winding * ON/OFF control provides constant efficiency down to very light loads - ideal for mandatory CEC efficiency regulations and 1 W PC standby requirements Applications * Applications with high peak-to-continuous power demands - DVDs, PVRs, active speakers (e.g. PC audio), audio amplifiers, modems, photo printers * Applications with high power demands at startup (large output capacitance or motor loads) - PC standby, low voltage motor drives www.powerint.com (R) AC IN + DC OUT D EN/UV BP/M TinySwitch-PK S PI-4266-010906 Figure 1. Typical Peak Power Application. Output Power Table 230 VAC 15% Product3 TNY375PN TNY376PN TNY377PN TNY378PN TNY379PN TNY380PN Open Adapter1 Frame2 8.5 W 10 W 13 W 16 W 18 W 20 W 15 W 19 W 23.5 W 28 W 32 W 36.5 W 85-265 VAC Open Frame2 11.5 W 15 W 18 W 21.5 W 25 W 28.5 W Peak 12.5 W 17 W 23 W 27 W 31 W 35 W Peak Adapter1 16.5 W 22 W 28 W 34 W 39 W 45 W 6W 7W 8W 10 W 12 W 14 W Table 1. Output Power Table. Notes: 1. Minimum continuous power in a typical non-ventilated enclosed adapter measured at +50 C ambient. Use of an external heatsink will increase power capability. 2. Minimum continuous power in an open frame design (see Key Applications Considerations). 3. Packages: P: DIP-8C. Lead free only. See Part Ordering Information. Description TinySwitch-PK incorporates a 700 V MOSFET, oscillator, highvoltage switched current source, current limit (user selectable), and thermal shutdown circuitry. A unique peak mode feature boosts current limit and frequency for peak load conditions. The boosted current limit provides the peak output power while the increased peak mode frequency ensures the transformer can be sized for continuous load conditions rather than peak power demands. May 2007 TNY375-380 BYPASS/ MULTI-FUNCTION (BP/M) REGULATOR 5.85 V LINE UNDER-VOLTAGE 25 mA AUTORESTART COUNTER RESET DRAIN (D) 115 mA FAULT PRESENT + BYPASS PIN UNDER-VOLTAGE BYPASS CAPACITOR SELECT AND 5.85 V 4.9 V CURRENT LIMIT STATE MACHINE VI LIMIT CURRENT LIMIT COMPARATOR ENABLE + 1.0 V + VT JITTER 2X CLOCK DCMAX OSCILLATOR THERMAL SHUTDOWN ENABLE/ UNDERVOLTAGE (EN/UV) 1.0 V 6.4 V OVP LATCH RESET S Q R Q LEADING EDGE BLANKING SOURCE (S) PI-4550-121406 Figure 2 Functional Block Diagram. Pin Functional Description DRAIN (D) Pin: This pin is the power MOSFET drain connection. It provides internal operating current for both start-up and steady-state operation. BYPASS/MULTI-FUNCTION (BP/M) Pin: This pin has multiple functions: 1. It is the connection point for an external bypass capacitor for the internally generated 5.85 V supply. 2. It is a mode selector for the current limit value, depending on the value of the capacitance added. Use of a 0.1 mF capacitor results in the standard current limit value. Use of a 1 mF capacitor results in the current limit being reduced to that of the next smaller device size. Use of a 10 mF capacitor results in the current limit being increased to that of the next larger device. 3. It provides a shutdown function. When the current into the bypass pin exceeds 7 mA, the device latches off until the BP/M voltage drops below 4.9 V, during a power down or when a line undervoltage is detected. This can be used to provide an output overvoltage function with a Zener diode connected from the BP/M pin to a bias winding supply. P Package (DIP-8C) EN/UV BP/M 1 2 8 7 6 S S S S D 4 5 PI-4348-032806 Figure 3. Pin Configuration. ENABLE/UNDERVOLTAGE (EN/UV) Pin: This pin has dual functions: enable input and line undervoltage sense. During normal operation, switching of the power MOSFET is controlled by this pin. MOSFET switching is terminated when a current greater than a threshold current is drawn from this pin. Switching resumes when the current being 2 Rev. A 05/07 www.powerint.com TNY375-380 pulled from the pin drops to less than a threshold current. A modulation of the threshold current reduces group pulsing. The threshold current is between 75 mA and 115 mA. The EN/UV pin also senses line undervoltage conditions through an external resistor connected to the DC line voltage. If there is no external resistor connected to this pin, TinySwitch-PK detects its absence and disables the line undervoltage function. SOURCE (S) Pin: This pin is internally connected to the output MOSFET source for high voltage power return and control circuit common. the frequency jitter is set to 1 kHz to optimize EMI reduction for both average and quasi-peak emissions. The frequency jitter should be measured with the oscilloscope triggered at the falling edge of the DRAIN waveform. The waveform in Figure 4 illustrates the frequency jitter with an oscillator frequency of 264 kHz. Enable Input and Current Limit State Machine The enable input circuit at the EN/UV pin consists of a low impedance source follower output set at 1.2 V. The current through the source follower is limited to 115 mA. When the current out of this pin exceeds the threshold current, a low logic level (disable) is generated at the output of the enable circuit until the current out of this pin is reduced to less than the threshold current. This enable circuit output is sampled at the beginning of each cycle on the rising edge of the clock signal. If high, the power MOSFET is turned on for that cycle (enabled). If low, the power MOSFET remains off (disabled). Since the sampling is done only at the beginning of each cycle, subsequent changes in the EN/UV pin voltage or current during the remainder of the cycle are ignored. When a cycle is disabled, the EN/UV pin is sampled at 264 kHz. This faster sampling enables the power supply to respond faster without being required to wait for completion of the full period. The current limit state machine reduces the current limit by discrete amounts at light loads when TinySwitch-PK is likely to switch in the audible frequency range. The lower current limit raises the effective switching frequency above the audio range and reduces the transformer flux density, including the associated audible noise. The state machine monitors the sequence of enable events to determine the load condition and adjusts the current limit level accordingly in discrete amounts. Under most operating conditions (except when close to noload), the low impedance of the source follower keeps the voltage on the EN/UV pin from going much below 1.2 V in the disabled state. This improves the response time of the optocoupler that is usually connected to this pin. 5.85 V Regulator and 6.4 V Shunt Voltage Clamp The 5.85 V regulator charges the bypass capacitor connected to the BYPASS pin to 5.85 V by drawing a current from the voltage on the DRAIN pin whenever the MOSFET is off. The BYPASS/MULTI-FUNCTION pin is the internal supply voltage node. When the MOSFET is on, the device operates from the energy stored in the bypass capacitor. Extremely low power consumption of the internal circuitry allows the TNY375 and TNY376 to operate continuously from current taken from the DRAIN pin. A bypass capacitor value of 0.1 mF is sufficient for both high frequency decoupling and energy storage. In addition, there is a 6.4 V shunt regulator clamping the BYPASS/MULTI-FUNCTION pin at 6.4 V when current is provided to the BYPASS/MULTI-FUNCTION pin through an external resistor. This facilitates powering of TinySwitch-PK externally through a bias winding as required for TNY377-380. Powering the TinySwitch-PK externally in this way also decreases the no-load consumption to below 60 mW. TinySwitch-PK Functional Description TinySwitch-PK combines a high voltage power MOSFET switch with a power supply controller in one device. Unlike conventional PWM (pulse width modulator) controllers, it uses a simple ON/OFF control to regulate the output voltage. The controller consists of an oscillator, enable circuit (sense and logic), current limit state machine, 5.85 V regulator, BYPASS/ MULTI-FUNCTION pin undervoltage, overvoltage circuit, and current limit selection circuitry, over-temperature protection, current limit circuit, leading edge blanking, and a 700 V power MOSFET. TinySwitch-PK incorporates additional circuitry for line undervoltage sense, auto-restart, adaptive switching cycle on-time extension, and frequency jitter. Figure 2 shows the functional block diagram with the most important features. Oscillator The typical oscillator frequency is internally set to an average of 264 kHz (at the highest current limit level). Two signals are generated from the oscillator: the maximum duty cycle signal (DCMAX) and the clock signal that indicates the beginning of each cycle. The oscillator incorporates circuitry that introduces a small amount of frequency jitter, typically 3% of the oscillator frequency, to minimize EMI emission. The modulation rate of PI-4539-120406 600 500 VDRAIN 400 300 200 100 0 272 kHz 256 kHz 0 Figure 4. Frequency Jitter. 2.5 5 Time (s) 3 www.powerint.com Rev. A 05/07 TNY375-380 BYPASS/MULTI-FUNCTION Pin Undervoltage The BYPASS/MULTI-FUNCTION pin undervoltage circuitry disables the power MOSFET when the BYPASS/MULTIFUNCTION pin voltage drops below 4.9 V in steady state operation. Once the BYPASS/MULTI-FUNCTION pin voltage drops below 4.9 V in steady state operation, it must rise back to 5.85 V to enable (turn-on) the power MOSFET. Over Temperature Protection The thermal shutdown circuitry senses the die temperature. The threshold is typically set at 142 C with 75 C hysteresis. When the die temperature rises above this threshold, the power MOSFET is disabled and remains disabled, until the die temperature falls by 75 C, at which point it is re-enabled. A large hysteresis of 75 C (typical) is provided to prevent overheating of the PC board due to a continuous fault condition. Current Limit The current limit circuit senses the current in the power MOSFET. When this current exceeds the internal threshold (ILIMIT ), the power MOSFET is turned off for the remainder of that cycle. The current limit state machine reduces the current limit threshold by discrete amounts under medium and light loads. The leading edge blanking circuit inhibits the current limit comparator for a short time (tLEB) after the power MOSFET is turned on. This leading edge blanking time has been set so that current spikes caused by typical capacitance and secondary-side rectifier reverse recovery time will not cause premature termination of the switching pulse. Auto-Restart In the event of a fault condition such as output overload, output short circuit, or an open loop condition, TinySwitch-PK enters into auto-restart operation. An internal counter clocked by the oscillator is reset every time the EN/UV pin is pulled low. If the EN/UV pin is not pulled low for 8192 switching cycles (or 32 ms), the power MOSFET switching is normally disabled for 1 second (except in the case of line undervoltage condition, in which case it is disabled until the condition is removed). The PI-4320-030106 auto-restart alternately enables and disables the switching of the power MOSFET until the fault condition is removed. Figure 5 illustrates auto-restart circuit operation in the presence of an output short circuit. In the event of a line undervoltage condition, the switching of the power MOSFET is disabled beyond its normal 1 second until the line undervoltage condition ends. Adaptive Switching Cycle On-Time Extension Adaptive switching cycle on-time extension keeps the cycle on until current limit is reached, instead of prematurely terminating after the DCMAX signal goes low. This feature reduces the minimum input voltage required to maintain regulation, typically extending hold-up time and minimizing the size of bulk capacitor required. The on-time extension is disabled during the startup of the power supply, and after auto-restart, until the power supply output reaches regulation. Line Undervoltage Sense Circuit The DC line voltage can be monitored by connecting an external resistor from the DC line to the EN/UV pin. During power-up or when the switching of the power MOSFET is disabled in auto-restart, the current into the EN/UV pin must exceed 25 mA to initiate switching of the power MOSFET. During power-up, this is accomplished by holding the BYPASS/ MULTI-FUNCTION pin to 4.9 V while the line undervoltage condition exists. The BYPASS/MULTI-FUNCTION pin then rises from 4.9 V to 5.85 V when the line undervoltage condition goes away. Once MOSFET switching is enabled, the DC line voltage is ignored unless the power supply enters auto-restart mode in the event of a fault condition. When the switching of the power MOSFET is disabled in auto-restart mode and a line undervoltage condition exists, the auto-restart counter is stopped. This stretches the disable time beyond its normal 1 second until the line undervoltage condition ends. The line undervoltage circuit also detects when there is no external resistor connected to the EN/UV pin (less than ~1 mA into the pin). In this case the line undervoltage function is disabled. TinySwitch-PK Operation TinySwitch-PK devices operate in the current limit mode. When enabled, the oscillator turns the power MOSFET on at the beginning of each cycle. The MOSFET is turned off when the current ramps up to the current limit or when the DCMAX limit is reached (applicable when On-Time Extension is disabled). Since the highest current limit level and frequency of a TinySwitch-PK design are constant, the power delivered to the load is proportional to the primary inductance of the transformer and peak primary current squared. Hence, designing the supply involves calculating the primary inductance of the transformer for the maximum output power required. If the TinySwitch-PK is appropriately chosen for the power level, the current in the calculated inductance will ramp up to current limit before the DCMAX limit is reached. 300 200 100 0 10 5 0 V DRAIN V DC-OUTPUT 0 Figure 5. Auto-Restart Operation. 1000 2000 Time (ms) Rev. A 05/07 www.powerint.com TNY375-380 The EN/UV pin signal is generated on the secondary by comparing the power supply output voltage with a reference voltage. The EN/UV pin signal is high when the power supply output voltage is less than the reference voltage. In a typical implementation, the EN/UV pin is driven by an optocoupler. The collector of the optocoupler transistor is connected to the EN/UV pin, and the emitter is connected to the SOURCE pin. The optocoupler LED is connected in series with a Zener diode across the DC output voltage to be regulated. When the output voltage exceeds the target regulation voltage level (optocoupler LED voltage drop plus Zener voltage), the optocoupler LED will start to conduct, pulling the EN/UV pin low. The Zener diode can be replaced by a TL431 reference circuit for improved accuracy. ON/OFF Operation with Current Limit State Machine The internal clock of the TinySwitch-PK runs at all times. At the beginning of each clock cycle, it samples the EN/UV pin to decide whether or not to implement a switch cycle, and based on the sequence of samples over multiple cycles, it determines the appropriate current limit. At high loads, the state machine sets the current limit to its highest value. With TinySwitch-PK, when the state machine sets the current limit to its highest value, the oscillator frequency is also doubled, providing the unique peak mode operation. At lighter loads, the state machine sets the current limit to reduced values. At these lower current limit levels, the oscillator frequency returns to the standard value. At near maximum load, TinySwitch-PK will conduct during nearly all of its clock cycles (Figure 6). At slightly lower load, it will "skip" additional cycles in order to maintain voltage regulation at the power supply output (Figure 7). At medium loads, more cycles will be skipped, the current limit will be V EN CLOCK DC MAX I DRAIN V DRAIN PI-2749-082305 Figure 6. Operation at Near Maximum Loading (fOSC 264 kHz). V EN CLOCK DC MAX I DRAIN V EN CLOCK V DRAIN DC MAX PI-2667-082305 Figure 7. Operation at Moderately Heavy Loading (fOSC 264 kHz). I DRAIN Enable Function TinySwitch-PK senses the EN/UV pin to determine whether or not to proceed with the next switching cycle. The sequence of cycles is used to determine the current limit. Once a cycle is started, it always completes the cycle (even when the EN/UV pin changes state halfway through the cycle). This operation results in a power supply in which the output voltage ripple is determined by the output capacitor, amount of energy per switch cycle, and the delay of the feedback. V DRAIN PI-4540-050407 Figure 8. Operation at Medium Loading (fOSC 132 kHz). 5 www.powerint.com Rev. A 05/07 TNY375-380 PI-2381-1030801 200 V EN CLOCK D 100 0 10 V DC-INPUT MAX 5 0 V BYPASS I DRAIN 400 200 0 0 1 2 V DRAIN Time (ms) V DRAIN Figure 11. Power-up Without Optional External UV Resistor Connected to EN/UV Pin. PI-2348-030801 PI-4541-042507 Figure 9. Operation at Very Light Load (fOSC 132 kHz). 200 100 PI-2383-030801 V DC-INPUT 200 100 0 V DC-INPUT 0 400 300 10 5 0 0 400 200 0 0 1 2 200 100 0 400 300 200 100 0 0 2.5 5 V DRAIN V DC-INPUT V DRAIN V BYPASS 200 100 V DRAIN 0 .5 1 Time (s) Figure 12. Normal Power-down Timing (Without UV Resistor). PI-2395-030801 Time (ms) Figure 10. Power-up With Optional External UV Resistor (4 MW) Connected to EN/UV Pin. Time (s) Figure 13. Slow Power-down Timing With Optional External (4 MW) UV Resistor Connected to EN/UV Pin. 6 Rev. A 05/07 www.powerint.com TNY375-380 reduced, and the clock frequency is reduced to half that at the highest current limit level (Figure 8). At very light loads, the current limit will be reduced even further (Figure 9). Only a small percentage of cycles will occur to satisfy the power consumption of the power supply. The response time of the ON/OFF control scheme is very fast compared to PWM control. This provides tight regulation and excellent transient response. Power Up/Down The TinySwitch-PK requires only a 0.1 mF capacitor on the BYPASS/MULTI-FUNCTION pin to operate with standard current limit. Because of its small size, the time to charge this capacitor is kept to an absolute minimum, typically 0.6 ms. The time to charge will vary in proportion to the BYPASS/MULTIFUNCTION pin capacitor value when selecting different current limits. Due to the high bandwidth of the ON/OFF feedback, there is no overshoot at the power supply output. When an external resistor (4 MW) is connected from the power supply positive DC input to the EN/UV pin, the power MOSFET switching will be delayed during power-up until the DC line voltage exceeds the threshold (100 V). Figures 10 and 11 show the power-up timing waveform in applications with and without an external resistor (4 MW) connected to the EN/UV pin. During power-down, when an external resistor is used, the power MOSFET will switch for 32 ms after the output loses regulation. The power MOSFET will then remain off without any glitches since the undervoltage function prohibits restart when the line voltage is low. Figure 12 illustrates a typical power-down timing waveform. Figure 13 illustrates a very slow power-down timing waveform, as in standby applications. The external resistor (4 MW) is connected to the EN/UV pin in this case to prevent unwanted restarts. With the TNY375 and TNY376, no bias winding is needed to provide power to the chip because it draws the power directly from the DRAIN pin (see Functional Description above). This eliminates the cost of a bias winding and associated components. For the TNY377-380 or for applications that require very low no-load power consumption (50 mW), a resistor from a bias winding to the BYPASS/MULTI-FUNCTION pin can provide the power to the chip. The minimum recommended current supplied is IS2 + IDIS. The BYPASS/MULTI-FUNCTION pin in this case will be clamped at 6.4 V. This method will eliminate the power draw from the DRAIN pin, thereby reducing the no-load power consumption and improving full-load efficiency. Current Limit Operation Each switching cycle is terminated when the DRAIN current reaches the current limit of the device. Current limit operation provides good line ripple rejection and relatively constant power delivery independent of input voltage. BYPASS/MULTI-FUNCTION Pin Capacitor The BYPASS/MULTI-FUNCTION pin can use a ceramic capacitor as small as 0.1 mF for decoupling the internal power supply of the device. A larger capacitor size can be used to adjust the current limit. A 1 mF BP/M pin capacitor will select a lower current limit equal to the standard current limit of the next smaller device, and a 10 mF BP/M pin capacitor will select a higher current limit equal to the standard current limit of the next larger device. The TNY375 and TNY376 MOSFETs do not have the capability to match the current limit of the next larger devices in the family. The current limit is therefore increased to the maximum capability of their respective MOSFETs. The higher current limit level of the TNY380 is set to 1105 mA typical. The smaller current limit of the TNY375 is set to 325 mA. 7 www.powerint.com Rev. A 05/07 TNY375-380 C5 330 pF 250 VAC T1 EEL19 D1 FR106 L 85-265 VAC N D3 1N4007 D4 1N4007 F1 3.15 A D2 FR106 C1 22 F 400 V L1 5 mH 6 D6 UF4003 L2 3.3 H +12 V, 0.64 A VR1 P6KE180A C2 22 F 400 V N.C. R1 100 C3 10 nF 1 kV 1 11 D7 1N5819 L3 3.3 H R6 20 k 1% +5.0 V, 0.6 A R2 47 4 3 7 D8 SB340 L4 3.3 H +3.3 V, 0.6 A D5 FR106 5 8,9,10 C9 1000 F 10 V 12 C7 1000 F 25 V C5 220 F 25 V JP2 R4 200 1/2 W C6 100 F 25 V C10 470 F 10 V RTN C8 470 F 10 V -12 V, 0.03 A TinySwitch-PK U1 D TNY376P EN/UV BP U2B LTV817A D9 UF4003 JP1 C11 47 F 25 V R3 1 1/2 W C12 220 F 25 V U2A LTV817A C14 100 nF 50 V S C4 10 F 50 V R5 1k R7 6.34 k 1% C13 10 F 50 V R9 3.3 k U3 L431 2% R8 10 k 1% PI-4673-051107 Figure 14. TNY376P, Four Output, 7.5 W, 13 W Peak Universal Input Power Supply. Applications Examples The circuit shown in Figure 14 is a low cost universal AC input, four-output flyback power supply utilizing a TNY376. The continuous output power is 7.5 W with a peak of 13 W. The output voltages are 3.3 V, 5 V, 12 V, and -12 V. The rectified and filtered input voltage is applied to the primary winding of T1. The other side of the transformer's primary is driven by the integrated MOSFET in U1. Diode D5, C3, R1, R2, and VR1 compose the clamp circuit, limiting the leakage inductance turn-off voltage spike on the DRAIN pin to a safe value. The use of a combination Zener clamp and parallel RC optimizes both EMI and energy efficiency. Both the 3.3 V and 5 V outputs are sensed through resistors R6 and R7. The voltage across R8 is regulated to 2.5 V by reference IC U3. If the voltage across R8 begins to exceed 2.5 V, then current will flow in the LED inside the optocoupler U2, driven by the cathode of U3. This will cause the transistor of the optocoupler to sink current from the EN/UV pin of U1. When the current exceeds the ENABLE pin threshold current, the next switching cycle is inhibited. Conversely, when the voltage across resistor R8 falls below 2.5 V, and the current out of the ENABLE pin is below the threshold, a conduction cycle is allowed to occur. By adjusting the number of enabled cycles, regulation is maintained. As the load reduces, the number of enabled cycles decreases, lowering the effective switching frequency and scaling switching losses with load. This provides almost constant efficiency down to very light loads, ideal for meeting energy efficiency requirements. 8 Rev. A 05/07 The input filter circuit (C1, L1 and C2) reduces conducted EMI. To improve common mode EMI, this design makes use of E-ShieldTM shielding techniques in the transformer, reducing common mode displacement currents, and reducing EMI. These techniques, combined with the frequency jitter of TNY376, give excellent EMI performance, with this design achieving >10 dBmV of margin to EN55022 Class B conducted EMI limits. For design flexibility, the value of C4 can be selected to pick one of the three current limit options in U4. Doing so allows the designer to select the current limit appropriate for the application. * * * Standard current limit is selected with a 0.1 mF BP/M pin capacitor and is the normal choice for typical applications. When a 1 mF BP/M pin capacitor is used, the current limit is reduced, offering reduced RMS device currents and therefore improved efficiency, but at the expense of maximum power capability. This is ideal for thermally challenging designs where dissipation must be minimized. When a 10 mF BP/M pin capacitor is used, the current limit is increased, extending the power capability for applications requiring higher peak power or continuous power where the thermal conditions allow. Further flexibility comes from the current limits between adjacent TinySwitch-PK family members being compatible. The reduced current limit of a given device is equal to the standard current limit of the next smaller device, and the increased current limit is equal to the standard current limit of the next larger device. www.powerint.com TNY375-380 Key Application considerations TinySwitch-PK Design Considerations Output Power Table Data sheet maximum output power table (Table 1) represents the maximum practical continuous output power level that can be obtained under the following assumed conditions: 1. The minimum DC input voltage is 100 V or higher for 85 VAC input, or 220 V or higher for 230 VAC input or 115 VAC with a voltage doubler. The value of the input capacitance should be sized to meet these criteria for AC input designs. 2. Efficiency of 75%. 3. Minimum data sheet value of I2f. 4. Transformer primary inductance tolerance of 10%. 5. Reflected output voltage (VOR) of 135 V. 6. Voltage only output of 12 V with an ultrafast PN rectifier diode 7. Continuous conduction mode operation with transient KP* value of 0.25. 8. Increased current limit is selected for peak and open frame power columns and standard current limit for adapter columns. 9. The part is board mounted with SOURCE pins soldered to a sufficient area of copper to keep the SOURCE pin temperature at or below 110 C. 10. Ambient temperature of 50 C for open frame designs and 40 C for sealed adapters. *KP. Below a value of 1, KP is the ratio of ripple to peak primary current. A transient KP limit of 0.25 is recommended to avoid premature termination of switching cycles due to initial current limit (IINIT ) being exceeded, which reduces maximum output power capability. Peak Output Power Table 230 VAC 15% Product TNY375PN TNY376PN TNY377PN TNY378PN TNY379PN TNY380PN Table 2. 85-265 VAC ILIMITPEAKred ILIMITPEAKred ILIMITPEAK 14.5 W 19 W 23 W 27.5 W 31.5 W 36 W ILIMITPEAKinc ILIMITPEAK 11.5 W 15 W 18 W 21.5 W 25 W 28 W ILIMITPEAKinc 8.5 W 10 W 13 W 16 W 18 W 20 W 16.5 W 22 W 28 W 34 W 39 W 45 W 5.5 W 6W 8W 10 W 12 W 14 W 12.5 W 17 W 23 W 27 W 31 W 35 W Peak Output Power Capability vs Current Limit Mode Selection. The values shown in Table 1 for peak power assume operation in ILIMITPEAKinc. For reference, Table 2 provides peak output powers for each family member at all three selectable current limit modes. For both Table 1 and Table 2, the peak output power values are limited electronically, based on minimum device I2f. Stated differently, with sufficient heatsinking, these values could be delivered indefinitely, but in most cases this would be impractical. Adapter and open frame power values are thermally limited and represent the practical continuous (or average) output power in two common thermal environments. Over Voltage Protection The output overvoltage protection provided by TinySwitch-PK uses an internal latch that is triggered by a threshold current of approximately 7 mA into the BYPASS pin. In addition to an internal filter, the BYPASS pin capacitor forms an external filter, providing noise immunity from inadvertent triggering. For the bypass capacitor to be effective as a high frequency filter, it C9 2.2 nF 250 VAC T1 EFD25 D1 1N4007 L 185-265 VAC N D3 1N4007 D4 1N4007 L1 1 mH F1 3.15 A D2 1N4007 C1 10 F 400 V C2 22 F 400 V 1 9,10 C3 D5 SB560 1000 F 16 V C4 1000 F 16 V L2 3.3 H C5 220 F 16 V +12 V VR3 P6KE170A C8 10 nF 1 kV R7 22 1/2 W 3 6,7,8 RTN R9 3.9 M R1 1k R10 3.9 M D7 UF4007 5 R4 20 D6 UF4004 VR1 BZX55B11 11 V, 2% 2 VR2 1N5251B, 22 V TinySwitch-PK U1 D TNY380P R5 47 1/8 W C7 1F 50 V EN/UV BP R6 21 k 1% U2 PC817A R2 390 1/8 W S C6 10 F 50 V R3 2k 1/8 W PI-4674-051707 Figure 15. Single 230 VAC Input 20 W Continuous and 45 W Peak Power Supply Using TNY380P. 9 www.powerint.com Rev. A 05/07 TNY375-380 should be located as close as possible to the SOURCE and BYPASS pins of the device. For best performance of the OVP function, it is recommended that a relatively high bias winding voltage is used, in the range of 15 V-30 V. This minimizes the error voltage on the bias winding due to leakage inductance and also ensures adequate voltage during no-load operation from which to supply the IC device consumption. Selecting the Zener diode voltage to be approximately 6 V above the bias winding voltage (28 V for 22 V bias winding) gives good OVP performance for most designs but can be adjusted to compensate for variations in leakage inductance. Adding additional filtering can be achieved by inserting a low value (10 W to 47 W) resistor in series with the bias winding diode and/or the OVP Zener, as shown by R4 and R5 in Figure 15. The resistor in series with the OVP Zener also limits the maximum current into the BYPASS pin. Reducing No-load Consumption With the exception of the TNY375 and TNY376, a bias winding must be used to provide supply current for the IC. This has the additional benefit of reducing the typical no-load consumption to <60 mW. Select the value of the resistor (R6 in Figure 15) to provide the data sheet supply current equal to IS2 + |IDIS|. Although in practice the bias voltage falls at low load, the reduction in supply current through R6 is balanced against the reduced IC consumption as the effective switching frequency reduces with load. Audible Noise The cycle skipping mode of operation used in the TinySwitch-PK devices can generate audio frequency components in the transformer. To limit this audible noise generation, the transformer should be designed such that the peak core flux density is below 3000 Gauss (300 mT). Following this guideline, and using the standard transformer production technique of dip varnishing practically eliminates audible noise. Vacuum impregnation of the transformer should not be used due to the high primary capacitance and increased losses that results. Ceramic capacitors that use dielectrics such as Z5U, when used in clamp circuits, may also generate audio noise. If this is the case, try replacing them with a capacitor having a different dielectric or construction such as the film foil or metallized foil type. Bypass Capacitor (CBP) The BYPASS pin capacitor should be located as near as possible to the BYPASS and SOURCE pins using a Kelvin connection. No power current should flow through traces connected to the BYPASS pin capacitor or optocoupler. If using SMD components, a capacitor can be placed underneath the package directly between BP and SOURCE pins. When using a capacitor value of 1 mF or 10 mF to select the reduced or increased current limit mode, it is recommended that an additional 0.1 mF ceramic capacitor is placed directly between BP and SOURCE pins. Enable/Undervoltage Pin Node Connections The EN/UV pin is a low-current, low-voltage pin, and noise coupling can cause poor regulation and/or inaccurate line UV levels. Traces connected to the EN/UV pin must be routed away from any high current or high-voltage switching nodes, including the drain pin and clamp components. This also applies to the placement of the line undervoltage sense resistor (RUV ). Drain connected traces must not be routed underneath this component. TinySwitch-PK determines the presence of the UV resistor via a ~1 mA current into the EN/UV pin at startup. When the undervoltage feature is not used ensure that leakage current into the EN/UV pin is <<1mA. This prevents false detection of the presence of a UV resistor which may prevent correct start-up. As the use of no-clean flux may increase leakage currents (by reducing surface resistivity) care should be taken to follow the flux suppliers guidance, specifically avoiding flux contamination. Placing a 100 kW, 5% resistor between BP and EN/UV pins eliminates this requirement by feeding current >ILUV(MAX) into the EN/UV pin. Primary Loop Area The area of the primary loop that connects the input filter capacitor, transformer primary, and TinySwitch-PK device should be kept as small as possible. Primary Clamp Circuit A clamp is used to limit peak voltage on the DRAIN pin at turn off. This can be achieved by using an RCD clamp or a Zener and diode clamp across the primary winding. In all cases, to minimize EMI, care should be taken to minimize the loop length from the clamp components to the transformer and the TinySwitch-PK device. Thermal Considerations The four SOURCE pins are internally connected to the IC lead frame and provide the main path to remove heat from the device. Therefore all the SOURCE pins should be connected to a copper area underneath the TinySwitch-PK integrated circuit to act not only as a single point ground, but also as a heatsink. As this area is connected to the quiet source node, it should be maximized for good heatsinking. Similarly, for axial output diodes, maximize the PCB area connected to the cathode. TinySwitch-PK Layout Considerations Single Point Grounding Use a single point ground connection from the input filter capacitor to the area of copper connected to the SOURCE pins. When used as an auxiliary supply in a larger converter, a local DC bus decoupling capacitor is recommended. A value of 100 nF is typical. The bias winding should be returned directly to the input or decoupling capacitor. This routes surge currents away from the device during common mode line surge events. 10 Rev. A 05/07 www.powerint.com TNY375-380 Return bias winding directly to input capacitor Safety Spacing Y1Capacitor Copper area for heat sinking + HV Maximize hatched copper areas ( ) for optimum heatsinking Output Rectifier Input Filter Capacitor PRI BIAS D TinySwitch-PK - PRI S S S EN/UV BP BIAS T r a n s f o r m e r SEC TOP VIEW S CBP RUV Bypass capacitor connection to device should be short Figure 16. Layout Considerations for TinySwitch-PK Using P Package. Optocoupler Route connections to EN/UV pin (including undervoltage resistor) away from drain connected traces - DC + OUT PI-4675-051507 Y-Capacitor The placement of the Y-capacitor should be directly from the primary input filter capacitor positive terminal to the common/ return terminal of the transformer secondary. Such a placement will route high magnitude common mode surge currents away from the TinySwitch-PK device. Note - if an input (C, L, C) EMI filter is used, then the inductor in the filter should be placed between the negative terminals on the input filter capacitors. Optocoupler Place the optocoupler physically close to the TinySwitch-PK device to minimize the primary side trace lengths. Keep the high current, high voltage drain and clamp traces away from the optocoupler to prevent noise pick up. Output Diode For best performance, the area of the loop connecting the secondary winding, the Output Diode, and the Output Filter Capacitor should be minimized. In addition, for axial diodes, sufficient copper area should be provided at the anode and cathode terminal of diode for heatsinking. A larger area is preferred at the quiet cathode terminal. A large anode area can increase high frequency radiated EMI. Quick Design Checklist As with any power supply design, all TinySwitch-PK designs should be verified on the bench to make sure that component specifications are not exceeded under worst case conditions. The following minimum set of tests is strongly recommended: 1. Maximum drain voltage - Verify the VDS does not exceed 650 V at highest input voltage and peak (overload) output power. The 50 V margin to the 700 V BVDSS specification gives margin for design variation. 2. Maximum drain current - At maximum ambient temperature, maximum input voltage, and peak output (overload) power, verify drain current waveforms for any signs of transformer saturation and excessive leading edge current spikes at startup. Repeat under steady state conditions and verify that the leading edge current spike event is below IINIT at the end of the tLEB(Min). Under all conditions the maximum drain current should be below the specified absolute maximum ratings. 3. Thermal Check - At specified maximum output power, minimum input voltage, and maximum ambient temperature, verify that the temperature specifications are not exceeded for TinySwitch-PK device, transformer, output diode, and output capacitors. Enough thermal margin should be allowed for part-to-part variation of the RDS(ON) of TinySwitch-PK device as specified in the data sheet. Under low-line maximum power, a maximum TinySwitch-PK device SOURCE pin temperature of 110 C is recommended to allow for these variations. Design Tools Up-to-date information on design tools can be found at the Power Integrations web site: www.powerint.com. 11 www.powerint.com Rev. A 05/07 TNY375-380 Absolute Maximum Ratings(1,5) DRAIN Voltage .............................................................................. -0.3 V to 700 V DRAIN Peak Current: TNY375 .............................................................. 0.6 A TNY376 .............................................................. 0.8 A TNY377 ...............................................................1.4 A TNY378 .............................................................. 2.2 A TNY379 .............................................................. 2.9 A TNY380.............................................................. 4.3 A EN/UV Voltage ................................................................................... -0.3 V to 9 V EN/UV Current ........................................................... .................................. 100 mA BP/M Voltage ......................................................................................-0.3 V to 9 V Storage Temperature .............................................................-65 C to 150 C Thermal Impedance Thermal Impedance: P Package: Notes: (qJA) ............................ .................... 70 C/W(2); 60 C/W(3) 1. Measured on the SOURCE pin close to plastic interface. (qJC)(1) ............................................... ............................11 C/W 2. Soldered to 0.36 sq. in. (232 mm2), 2 oz. (610 g/m2) copper clad. 3. Soldered to 1 sq. in. (645 mm2), 2 oz. (610 g/m2) copper clad. Operating Junction Temperature(3) ............................... -40 C to 150 C Lead Temperature(4) .....................................................................................260 C Notes: 1. All voltages referenced to SOURCE, TA = 25 C. 2. Normally limited by internal circuitry. 3. 1/16 in. from case for 5 seconds. 4. Maximum ratings specified may be applied one at a time without causing permanent damage to the product. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect product reliability. Parameter Control Functions Symbol Conditions SOURCE = 0 V; TJ = -0 to 125 C See Figure 17 (Unless Otherwise Specified) State Machine at Highest Current Limit Level TJ = 25 C All Lower Current Limit Levels TJ = 25 C S1 Open Min Typ Max Units Average pk-pk Jitter Average pk-pk Jitter 248 264 16 280 kHz 140 fOSC Output Frequency See Note A fOSC-Low Maximum Duty Cycle EN/UV Pin Upper Turnoff Threshold Current EN/UV Pin Voltage DCMAX IDIS 124 132 8 62 -150 65 -115 2.2 1.2 290 385 460 570 740 870 1100 520 600 710 900 1060 1350 -90 2.6 1.6 % mA VEN IS1 IEN/UV = 25 mA IEN/UV = -25 mA EN/UV Current > IDIS (MOSFET Not Switching) See Note B TNY375 1.8 0.8 V mA DRAIN Supply Current IS2 EN/UV Open (MOSFET Switching at fOSC) See Note C TNY376 TNY377 TNY378 TNY379 TNY380 mA 12 Rev. A 05/07 www.powerint.com TNY375-380 Conditions SOURCE = 0 V; TJ = -0 to 125 C See Figure 17 (Unless Otherwise Specified) VBP/M = 0 V, TJ = 25 C See Note D, E VBP/M = 4 V, TJ = 25 C See Note D, E TNY375-378 TNY379-380 TNY375-378 TNY379-380 Parameter Control Functions (cont.) Symbol Min Typ Max Units ICH1 BP/M Pin Charge Current ICH2 BP/M Pin Voltage BP/M Pin Voltage Hysteresis BP/M Pin Shunt Voltage EN/UV Pin Line Undervoltage Threshold Circuit Protection VBP/M VBP/MH VSHUNT ILUV -8.3 -9.7 -5 -6.6 5.6 0.80 -5.4 -7.1 -3.5 -4.8 5.85 0.95 6.4 25 -2.5 -3.9 -1.5 -2.1 6.15 1.20 6.7 27.5 V V V mA mA See Note D IBP = 2 mA TJ = 25 C 6.0 22.5 TNY375 TJ = 25 C TNY376 TJ = 25 C Peak Current Limit (BP/M Capacitor = 0.1 mF) See Note E TNY377 TJ = 25 C TNY378 TJ = 25 C TNY379 TJ = 25 C TNY380 TJ = 25 C TNY375 TJ = 25 C TNY376 TJ = 25 C Peak Current Limit (BP/M Capacitor = 1 mF) See Note E TNY377 TJ = 25 C TNY378 TJ = 25 C TNY379 TJ = 25 C TNY380 TJ = 25 C di/dt = 72 mA/ms See Note F di/dt = 91 mA/ms See Note F di/dt = 117 mA/ms See Note F di/dt = 143 mA/ms See Note F di/dt = 169 mA/ms See Note F di/dt = 195 mA/ms See Note F di/dt = 72 mA/ms See Note F di/dt = 91 mA/ms See Note F di/dt = 117 mA/ms See Note F di/dt = 143 mA/ms See Note F di/dt = 169 mA/ms See Note F di/dt = 195 mA/ms See Note F 330 423 544 665 786 907 355 455 585 715 845 975 380 487 626 mA 765 904 1043 ILIMITPEAK 302 325 358 330 423 544 665 786 355 455 585 715 845 391 501 mA 644 787 930 ILIMITPEAKred 13 www.powerint.com Rev. A 05/07 TNY375-380 Conditions SOURCE = 0 V; TJ = -0 to 125 C See Figure 17 (Unless Otherwise Specified) TNY375 TJ = 25 C TNY376 TJ = 25 C Peak Current Limit (BP/M Capacitor = 10 mF) See Note E TNY377 TJ = 25 C TNY378 TJ = 25 C TNY379 TJ = 25 C TNY380 TJ = 25 C I2f = ILIMITPEAK(TYP)2 x fOSC(TYP) TJ = 25 C Power Coefficient If 2 Parameter Circuit Protection (cont.) Symbol Min Typ Max Units di/dt = 72 mA/ms See Note F di/dt = 91 mA/ms See Note F di/dt = 117 mA/ms See Note F di/dt = 143 mA/ms See Note F di/dt = 169 mA/ms See Note F di/dt = 195 mA/ms See Note F BP/M Capacitor = 0.1 mF 349 465 665 786 907 1028 0.9 x I2f 0.9 x I2f 0.9 x I2f 0.75 x ILIMIT(MIN) 190 375 500 715 845 975 1105 413 550 787 mA 930 1073 1216 1.12 x I2f 1.16 x I2f 1.16 x I2f mA ILIMITPEAKred I2f I2f = ILIMITPEAKred(TYP)2 x fOSC(TYP) TJ = 25 C I2f = ILIMITPEAKinc(TYP)2 x fOSC(TYP) TJ = 25 C BP/M Capacitor = 1 mF BP/M Capacitor = 10 mF I2f A2Hz I2f Initial Current Limit Leading Edge Blanking Time Current Limit Delay Thermal Shutdown Temperature Thermal Shutdown Hysteresis BP/M Pin Shutdown Threshold Current BP/M Pin Power-Up Reset Threshold Voltage IINIT tLEB tILD TSD TSDH ISD VBP/M(RESET) See Figure 17 TJ = 25 C, See Note G TJ = 25 C See Note G TJ = 25 C See Note G, H 235 200 ns ns 150 C C 9 mA 135 142 75 4 7 1.6 2.6 3.6 V 1 Rev. A 05/07 www.powerint.com TNY375-380 Conditions SOURCE = 0 V; TJ = -0 to 125 C See Figure 17 (Unless Otherwise Specified) TJ = 25 C TJ = 100 C TJ = 25 C TJ = 100 C TJ = 25 C TJ = 100 C TJ = 25 C TJ = 100 C TJ = 25 C TJ = 100 C TJ = 25 C TJ = 100 C TNY375-376 TNY377-378 TNY379-380 VDS = 375 V, TJ = 50 C See Note G, I 700 50 tAR DCAR TJ = 25 C See Note K TJ = 25 C 32 3 Parameter Output Symbol Min Typ Max Units TNY375 ID = 28 mA TNY376 ID = 35 mA 19 29 14 21 7.8 11.7 5.2 7.8 3.9 5.8 2.6 3.9 22 33 16 24 9.0 13.5 6.0 9.0 4.5 6.7 3.0 4.5 50 100 200 mA W ON-State Resistance TNY377 ID = 45 mA RDS(ON) TNY378 ID = 55 mA TNY379 ID = 65 mA TNY380 ID = 75 mA VBP/M = 6.2 V IDSS1 VEN/UV = 0 V VDS = 560 V TJ = 125 C See Note I VBP/M = 6.2 V VEN/UV = 0 V OFF-State Drain Leakage Current IDSS2 Breakdown Voltage DRAIN Supply Voltage Auto-Restart ON-Time At fOSC Auto-Restart Duty Cycle BVDSS 15 V V ms % VBP = 6.2 V, VEN/UV = 0 V, See Note J, TJ = 25 C 15 www.powerint.com Rev. A 05/07 TNY375-380 NOTES: A. For all BP/M pin capacitor values. B. IS1 is an accurate estimate of device controller current consumption at no-load, since operating frequency is so low under these conditions. Total device consumption at no-load is the sum of IS1 and IDSS2. C. Since the output MOSFET is switching, it is difficult to isolate the switching current from the supply current at the DRAIN. An alternative is to measure the BP/M pin current at 6.1 V. D. BP/M pin is not intended for sourcing supply current to external circuitry. E. To ensure correct current limit, it is recommended that nominal 0.1 mF / 1 mF / 10 mF capacitors are used. In addition, the BP/M capacitor value tolerance should be equal to or better than indicated below across the ambient temperature range of the target application. The minimum and maximum capacitor values are guaranteed by characterization. Tolerance Relative to Nominal Capacitor Value Min -60% -50% -50% Max +100% +100% NA Nominal BP/M Pin Cap Value 0.1 mF 1 mF 10 mF For current limit at other di/dt values, refer to Figure 24. Measurements made with device self-biased. This parameter is derived from characterization. This parameter is derived from the change in current limit measured at 1X and 4X of the di/dt shown in the ILIMIT specification. IDSS1 is the worst-case OFF state leakage specification at 80% of BVDSS and maximum operating junction temperature. IDSS2 is a typical specification under worst-case application conditions (rectified 265 VAC) for no-load consumption calculations. J. Breakdown voltage may be checked against minimum BVDSS specification by ramping the DRAIN pin voltage up to but not exceeding minimum BVDSS. K. Auto-restart on time has the same temperature characteristics as the oscillator (inversely proportional to frequency). F. G. H. I. 16 Rev. A 05/07 www.powerint.com TNY375-380 470 W 5W 470 W S S S S BP/M EN/UV D S2 S1 2 MW 50 V 10 V 0.1 mF 150 V NOTE: This test circuit is not applicable for current limit or output characteristic measurements. PI-4079-080905 Figure 17. General Test Circuit. (internal signal) tP DCMAX EN/UV VDRAIN tP = 1 fOSC PI-2364-012699 tEN/UV Figure 18. Duty Cycle Measurement. Figure 19. Output Enable Timing. 0.8 Figure 20. Current Limit Envelope at fOSC = 132 kHz. 17 www.powerint.com Rev. A 05/07 TNY375-380 PI-2213-012301 PI-2680-012301 1.1 1.2 1.0 0.8 0.6 0.4 0.2 0 Breakdown Voltage (Normalized to 25 C) 1.0 0.9 -50 -25 0 25 50 75 100 125 150 Output Frequency (Normalized to 25 C) -50 -25 0 25 50 75 100 125 Junction Temperature (C) Figure 21. Breakdown vs. Temperature. Junction Temperature (C) Figure 22. Frequency vs. Temperature. PI-4102-010906 Standard Current Limit (Normalized to 25 C) 1 0.8 0.6 0.4 0.2 0 -50 0 50 100 Normalized Current Limit 1.2 1.0 0.8 0.6 0.4 0.2 0 TNY375 TNY376 TNY377 TNY378 TNY379 TNY380 Normalized di/dt = 1 72 mA/s 91 mA/s 117 mA/s 143 mA/s 169 mA/s 195 mA/s Note: For the normalized current limit value, use the typical current limit specified for the appropriate BP/M capacitor. 150 1 2 3 4 Temperature (C) Figure 23. Standard Current Limit vs. Temperature. Normalized di/dt Figure 24. Current Limit vs. di/dt. PI-4267-120406 300 225 150 75 0 0 Drain Capacitance (pF) 375 Drain Current (mA) Scaling Factors: TNY375 1.0 TNY376 1.33 TNY377 2.33 TNY378 3.67 TNY379 4.87 TNY380 7.33 100 10 TCASE=25 C TCASE=100 C Scaling Factors: TNY375 1.0 TNY376 1.33 TNY377 2.33 TNY378 3.67 TNY379 4.87 TNY380 7.33 2 4 6 8 10 1 0 100 200 300 400 500 600 DRAIN Voltage (V) Figure 25. Output Characteristics. Drain Voltage (V) Figure 26. COSS vs. Drain Voltage. 18 Rev. A 05/07 www.powerint.com PI-4269-120406 450 1000 PI-4268-042707 1.2 1.4 TNY375-380 PI-4270-120406 Under-Voltage Threshold (Normalized to 25 C) 120 Power (mW) 90 60 30 Scaling Factors: TNY375 1.0 TNY376 1.33 TNY377 2.33 TNY378 3.67 TNY379 4.87 TNY380 7.33 1.0 0.8 0.6 0.4 0.2 0 0 200 400 600 0 -50 -25 0 25 50 75 100 125 DRAIN Voltage (V) Figure 27. Drain Capacitance Power. Junction Temperature (C) Figure 28. Undervoltage Threshold vs. Temperature. Part Ordering Information * TinySwitch Product Family * Series Number * Package Identifier P TNY 378 P N N Plastic DIP-8C Pure Matte Tin (Pb-Free) * Pin Finish DIP-8C -E- D S .004 (.10) .240 (6.10) .260 (6.60) Pin 1 -D.367 (9.32) .387 (9.83) .057 (1.45) .068 (1.73) (NOTE 6) .125 (3.18) .145 (3.68) .015 (.38) MINIMUM Notes: 1. Package dimensions conform to JEDEC specification MS-001-AB (Issue B 7/85) for standard dual-in-line (DIP) package with .300 inch row spacing. 2. Controlling dimensions are inches. Millimeter sizes are shown in parentheses. 3. Dimensions shown do not include mold flash or other protrusions. Mold flash or protrusions shall not exceed .006 (.15) on any side. 4. Pin locations start with Pin 1, and continue counter-clockwise to Pin 8 when viewed from the top. The notch and/or dimple are aids in locating Pin 1. Pin 3 is omitted. 5. Minimum metal to metal spacing at the package body for the omitted lead location is .137 inch (3.48 mm). 6. Lead width measured at package body. 7. Lead spacing measured with the leads constrained to be perpendicular to plane T. -T- SEATING PLANE .120 (3.05) .140 (3.56) .048 (1.22) .053 (1.35) .137 (3.48) MINIMUM .008 (.20) .015 (.38) .300 (7.62) BSC (NOTE 7) .300 (7.62) .390 (9.91) .100 (2.54) BSC .014 (.36) .022 (.56) T E D P08C PI-3933-100504 S .010 (.25) M www.powerint.com Rev. A 05/07 PI-2698-012301 150 1.2 19 Revision A Notes Release Final Datasheet Date 5/07 For the latest updates, visit our website: www.powerint.com Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS. Patent Information The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of Power Integrations patents may be found at www.powerint.com. Power Integrations grants its customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm. Life Support Policy POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein: 1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or death to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. The PI logo, TOPSwitch, TinySwitch, LinkSwitch, DPA-Switch, PeakSwitch, EcoSmart, Clampless, E-Shield, Filterfuse, StakFET, PI Expert and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. (c)2007, Power Integrations, Inc. Power Integrations Worldwide Sales Support Locations World Headquarters 5245 Hellyer Avenue San Jose, CA 95138, USA. Main: +1-408-414-9200 Customer Service: Phone: +1-408-414-9665 Fax: +1-408-414-9765 e-mail: usasales@powerint.com China (Shanghai) Rm 807-808A Pacheer Commercial Centre, 555 Nanjing Rd. West Shanghai, P.R.C. 200041 Phone: +86-21-6215-5548 Fax: +86-21-6215-2468 e-mail: chinasales@powerint.com China (Shenzhen) Rm 2206-2207, Block A, Electronics Science and Technology Bldg. 2070 Shennan Zhong Rd. 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